Circuit systems for generating signals locked to reference signals have long been known in which the frequency of an oscillator is regulated by means of a phase-locked loop (PLL). In such systems a phase comparison circuit is provided to which the reference signal is supplied at one input and the output signal of the system is supplied at another input. It is frequently necessary to generate a signal of which the frequency is a multiple of the frequency of the reference signal. In such cases a frequency divider is provided between the output of the controllable oscillator and the phase comparison circuit. Such circuits are utilized, for example, for the digital processing of video signals that are present as in analog form, more particularly for generating a sampling signal that is locked in frequency and phase with the horizontal synchronizing signal of the video signal.
It is also known to implement such circuits in digital circuit technology, in which case the output signal of the oscillator clocks a counter of which the content is interrogated at the rate of the reference signal. The counter's output, as further processed, is supplied as input magnitudes to a digitally controllable oscillator. The accuracy of the digital PLL circuits, however, is limited to one period of the signal to be generated, because of time and amplitude quantization.